1. Field of the Invention
The present invention relates to an interpolating programmable gain attenuator used in analog front ends.
2. Related Art
Broadband digital communication chips, such as cable modems and Ethernet chips, generally incorporate an analog front-end (AFE) on the chip, that comprises of an analog-to-digital converter (ADC) preceded by a programmable gain attenuator (PGA). The function of the PGA is to optimally use the dynamic range of the ADC.
FIG. 1 shows a conventional PGA. This circuit comprises a linear resistive attenuator (a resistive ladder), and is fully differential. The differential input voltage, denoted by vip and vin, is applied at the input of the PGA. Switches M1, M2, M3, . . . Mn (here, NMOS transistors, although PMOS transistors, or CMOS transmission gates, i.e., both an NMOS and PMOS transistor in parallel, can also be used) connect to all of the ‘taps’ of the PGA. On each side of the PGA, all-but-one switches M1, M2, M3, . . . Mn are ‘off’. The one pair of switches that is ‘on’, determines the magnitude of the differential output voltage, denoted by vop and von.
The size of the switches M1, M2, M3, . . . Mn is, in general, mainly determined by noise. To achieve low-noise performance, the on-resistance ron of the switches M1, M2, M3, . . . Mn has to be low. As a consequence, switches with a large width have to be used. Unfortunately, large switches introduce substantial parasitic capacitances, decreasing the achievable bandwidth of the PGA. Furthermore, the chip area of the PGA can become quite large. Since the PGA is integrated on-chip, the chip area occupied by the PGA is an important factor, i.e., lower area means lower cost.
FIG. 2 shows an improved conventional PGA, where always M pairs of consecutive switches are turned ‘on’ simultaneously (in FIG. 2, M=4). As a result, the switches can be M times less wide compared to the circuit shown in FIG. 1, improving both the bandwidth and area of the PGA.
The PGA is used to attenuate an input voltage arranging from, e.g., 100 millivolts to 4 volts down to a set value of 100 millivolts, e.g. Thus, in the PGA shown in FIGS. 1 and 2, by turning on a successive switch, the output voltage is gradually increased. The input voltage to the gates of the switches are usually digitally controlled.
The parasitic capacitance of the switches is usually dominant compared to the parasitic capacitance of the resistors. Typical parasitic capacitance of the switches is about 10–20 femtofarads. A typical value of each resistor R1 is several ohms. Typical dimensions for a resistor are about half a micron wide by a few microns long. The dimensions of the switches depend on process parameters, such as gate length (currently, about 0.09–0.35 microns). Typical value of the gate width is approximately 10–20 microns wide.
The PGA is used to attenuate the amplitude of the signal entering an amplifier or an A/D converter and often has as many as 500+ steps. Thus, using the structure illustrated in FIG. 1, for a 500 step PGA, 500×2 switches M1, M2, M3, . . . M500 and 500×2 resistors R1 need to be used. This requires a substantial area on the chip, e.g., 300×600 microns. Furthermore, because of the number of resistors and switches, they are usually not laid out in a straight line but are instead “folded” or laid out in zig zag pattern. The wiring trace length at the turning point of the zig zag pattern is longer than trace length elsewhere, introducing additional layout difficulties and potentially reducing the accuracy of the PGA. Also, the extra lengths of the trace at the zigzag can decrease the bandwidth of the PGA at that particular setting.